The invention relates to a method of manufacturing an electronic device comprising two layers of organic-containing material, said method comprising the steps of:
applying a first layer of organic-containing material to a substrate, PA1 covering the first layer of organic-containing material with a first layer of inorganic material, PA1 applying a second layer of inorganic material which is different from the inorganic material of the first layer, PA1 providing a first mask layer of resist having first openings, PA1 etching through the second layer of inorganic material at the location of the first openings, PA1 etching through the first layer of inorganic material at the location of the first openings, PA1 applying a second layer of organic-containing material, PA1 covering the second layer of organic-containing material with a third layer of inorganic material, PA1 applying a fourth layer of inorganic material which is different from the inorganic material of the third layer, PA1 providing a second mask layer of resist having second openings, PA1 etching through the fourth layer of inorganic material at the location of the second openings, PA1 etching through the third layer of inorganic material at the location of the second openings, PA1 etching through the second layer of organic-containing material at the location of the second openings. PA1 the second layer of inorganic material is etched in an etch process wherein the second inorganic material is selectively etched with respect to the first inorganic material, PA1 the first mask layer of resist is removed between etching through the second layer of inorganic material and etching through the first layer of inorganic material, PA1 the fourth layer of inorganic material is etched in an etch process wherein the fourth inorganic material is selectively etched with respect to the third inorganic material, PA1 the second mask layer of resist is removed between etching through the fourth layer of inorganic material and etching through the third layer of inorganic material, PA1 etching through the second layer of organic-containing material at the location of the second openings and etching through the first layer of organic-containing material at the location of the first openings take place simultaneously.
Such a method is known from EP-A-0 680 085. In one embodiment of the known method, an electrical connection is made between conductors on three metallisation levels in a semiconductor device, the connection being made through two layers of organic-containing dielectric material, each separating two adjacent metallisation levels. A first conductive layer is deposited on an insulating layer and subsequently patterned, whereby conductors on a first metallisation level are formed. Then an inorganic substrate encapsulation layer is deposited conformally on the exposed surfaces of the insulating layer and the conductors on the first metallisation level. Subsequently a first layer of organic-containing dielectric material, for example parylene, is deposited on and between the conductors on the first metallisation level. The first layer of organic-containing dielectric material is provided with an inorganic cap layer, for example silicon oxide, which in turn is covered with an inorganic hard mask layer, for example silicon nitride. After providing a mask layer of resist having openings, a via is etched through the inorganic hard mask layer, the inorganic cap layer and the first layer of organic-containing dielectric material at the location of the openings. Subsequently, an inorganic via passivation layer is applied to cover the exposed surfaces of the inorganic substrate encapsulation layer, the first layer of organic-containing dielectric material, the inorganic cap layer and the inorganic hard mask layer. In order to contact the underlying conductor on the first metallisation level, the inorganic via passivation layer is removed from the bottom of the via by anisotropic etching. During this step, the inorganic via passivation layer is removed from the top of the inorganic hard mask layer as well. The inorganic hard mask layer is applied in order to prevent etching of the inorganic cap layer during anisotropic etching. Next, a second conductive layer is applied to fill the via so as to form an electrical connection with the conductor on the first metallisation level at the bottom of the via. The part of the second conductive layer overlying the via is subsequently patterned, thereby forming conductors on a second metallisation level. Starting with the conformal deposition of a further inorganic substrate encapsulation layer and the application of a second layer of organic-containing dielectric material, the sequence of the above process steps is repeated once in order to finally end up with an electrical connection between the conductor on the first metallisation level, the conductor on the second metallisation level and a conductor on a third metallisation level, the connection being made through the first and the second layer of organic-containing dielectric material by means of vias filled with the conductive material.
A disadvantage of the known method is that it is difficult to control the dimensions of the vias.